Third level trigger of the DIRAC experiment

Abstract

A fast and complete programmable high level trigger processor for the DIRAC experiment at CERN was designed and arranged based on state-of-art Field Programmable Gate Array (FPGA) technology. The implemented logic was created from Monte Carlo simulation results and further checked with real experimental data. Correspondence between desired and implemented logic was proved previously by use of a complete digital pattern generator built also with FPGA technology. The resulting trigger processor provides a selection of charged particle pairs with a small relative momentum.