COMPARISON BETWEEN HAAR AND DAUBECHIES WAVELET TRANSFORMIONS ON FPGA TECHNOLOGY

Fatma H Elfouly,Moawad I M Dessouky,Salah Deyab,Mohamed I Mahmoud

doi:10.47839/ijc.6.3.447

Abstract

Recently, the Field Programmable Gate Array (FPGA) technology offers the potential of designing high performance systems at low cost. The discrete wavelet transform has gained the reputation of being a very effective signal analysis tool for many practical applications. However, due to its computation-intensive nature, current implementation of the transform falls short of meeting real-time processing requirements of most application. The objectives of this paper are implement the Haar and Daubechies wavelets using FPGA technology. In addition, the comparison between the Haar and Daubechies wavelets is investigated. The Bit Error Rat (BER) between the input audio signal and the reconstructed output signal for each wavelet is calculated. It is seen that the BER using Daubechies wavelet techniques is less than Haar wavelet. The design procedure has been explained and designed using the stat-of-art Electronic Design Automation (EDA) tools for system design on FPGA. Simulation, synthesis and implementation on the FPGA target technology has been carried out.

Highlights

The wavelet transform is an emerging signal processing technique that can be used to represent real-life non-stationary signals with high efficiency [1]
We present the components of our design using Electronic Design Automation (EDA) built in modules called
This paper proposed an efficient implementation of the Daubechies and Haar wavelet transform and compared between both of them using Field Programmable Gate Array (FPGA) technology

Summary

Introduction

The wavelet transform is an emerging signal processing technique that can be used to represent real-life non-stationary signals with high efficiency [1]. The wavelet transform is gaining momentum to become an alternative tool to traditional time-frequency representation techniques such as the discrete Fourier transform and the discrete cosine transform. Wavelet transform is mostly needed to be embedded in consumer electronics, and a single chip hardware implementation is more desirable than a multi-chip parallel system implementation. Several VLSI architectures have been proposed for the implementation of the discrete wavelet transform. Parhi and Nishitani proposed a folded architecture that has shorter latency [7], it requires complex routing and control network. Chakabarti [8] proposed a systolic architecture, and it requires many parallel hardware and complex routing. Custom VLSI circuits are inherently inflexible and their development is costly and time consuming, and they are not an attractive option for implementing the wavelet transform

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