Abstract

Device speed and functionality requirements are quickly forcing the semiconductor industry to incorporate copper and low-k dielectric materials. Compared to the commonly used aluminum metallization scheme on the traditional silicon dioxide and silicon nitride passivation, a Cu/low-k combination offers higher on-chip communication speed and a lower overall device cost. However, the low-k materials have intrinsically lower modulus and poorer adhesion compared to the commonly used dielectric materials. Thus, thermo-mechanical failure is one of the major challenges for development of a Cu/low-K large die flip chip package. In this paper, a two-dimensional plane strain analysis is performed on the diagonal cross-section of the package. A series of parametric study is performed to study the effect of bevel cut at die corner, effect of bevel cut depth, effect of filling materials of bevel cut, effect of Cu post bumps vs. lead-free bumps, effect of Cu post height and effect of Cu post diameter. Findings of these simulations could be used as a design consideration for the design of the Cu/low-k larger die flip chip package.

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