Optimization of reliability of copper-low-k flip chip package with variable interconnect compliance

Abstract

The trend toward finer pitch and higher performance integrated circuits (ICs) devices has driven the semiconductor industry to incorporate copper and low-k dielectric materials. However, the low-k materials have lower modulus and poorer adhesion compared to the common dielectric materials. Thus, thermo-mechanical failure is one of the major bottlenecks for development of fine-pitch, large-die Cu/low-k flip chip packages. In this paper, 3D finite element analyses were performed to investigate the reliability of 65 nm, 21times21 mm 9metal Cu/ low-k, chips with 150 mum interconnect pitch in a FCBGA package with a 750 mum die thickness and 1.0 mm substrate thickness. Three parametric cases involving different geometries of solder joints were analyze: (A) All 20 rows with spherical solder joints, (B) 10 hourglass joints followed by 10 spherical joints, and (C) 10 spherical joints followed by 10 hourglass joints. The spherical joints are stiffer than the hourglass joints. It was found that Case C gave the lowest inelastic energy dissipation (DeltaW) for the critical solder joint implying that Case C will have the longest fatigue life. It was also found that Case C gave the lowest maximum stress in the low-k material and it was further shown that reliability will be enhanced with decrease in die thickness and substrate thickness.