Thermoelectric Coolers for Hotspot Thermal Management of 3D Stacked Chips

Abstract

Three dimensional (3D) technologies with stacked chips have the potential to provide new chip architecture, improved device density, performance, efficiency, and bandwidth. Their increased power density also can become a daunting challenge for heat removal. Furthermore, power density can be highly non-uniform leading to time and space varying hotspots which can severely affect performance and reliability of the integrated circuits. Thus, it is important to mitigate thermal gradients on chip while considering the associated cooling costs. One method of thermal management currently under investigation is the use of superlattice thermoelectric coolers (TECs) which can be employed for on demand and localized cooling. In this paper, a detailed 3D thermal model of a stacked electronic package with two dies and four ultrathin integrated TECs is studied in order to investigate the efficacy of TECs in hot spot cooling for a 3D technology. We observe up to 14.6 °C of cooling at a hot spot inside the package by TECs. A strong vertical coupling has been observed between the TECs located in top and bottom dies. Bottom TECs can detrimentally heat the top hotspots in both steady state and transient operation. TECs need to be carefully placed inside the package to avoid such undesired heating. Thermal contact resistances between dies, inside the TEC module, and between the TEC and heat spreader are shown to have a crucial effect on TEC performance inside the package. We observed that square root current pulse can provide very efficient short-duration transient cooling at hotspots.