Hotspot Cooling in Stacked Chips Using Thermoelectric Coolers

Abstract

3-D technologies with stacked chips have the potential to provide new chip architecture, and improved device density, performance, efficiency, and bandwidth. The increased power density in 3-D technologies can become a daunting challenge for heat removal. Furthermore, power density can be highly nonuniform, leading to time- and space-varying hotspots, which can severely affect performance and reliability of integrated circuits. It is important to mitigate on-chip thermal gradients while considering the associated cooling costs. One efficient method of hotspot thermal management is to use superlattice thermoelectric coolers (TECs), which can provide on demand and localized cooling. In this paper, a detailed 3-D thermal model of a stacked electronic package with two dies and four ultrathin integrated TECs is developed to investigate the efficacy of TECs in hotspot cooling for 3-D technology. A strong vertical coupling has been observed between TECs located in top and bottom dies. Bottom TECs can significantly heat the top hotspots in both steady-state and transient operation. TECs need to be carefully placed inside the package to avoid such undesired heating. Thermal contact resistances between dies, inside the TEC module, and between TEC and heat spreader are shown to have a crucial effect on the TEC performance. We observe up to 5.6 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">°</sup> C of active hotspot cooling in steady state and 7.4 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">°</sup> C of active hotspot cooling using a square root current pulse.