Thermal-Mechanical Analysis of TSV Array in 2.5D Silicon Interposer

Abstract

With the development of integrated circuit towards the characteristics of the low-power consumption, miniaturization and high integration, three-dimensional integration technology based on Through-Silicon Via (TSV) comes into being. However, the thermal accumulation caused by the maximum stack density and the thermal stress caused by the mismatched thermal expansion coefficient between TSV surrounding materials will lead to the reliability problems such as circuit function failure and device performance drift. In this paper, the heat dissipation performance and thermal-mechanical reliability of TSV array in 2.5D silicon interposer were studied when the operation temperature is increased from 20°C to 100°C. Firstly, the influences of the geometrical parameters, such as the through hole radius, depth to width ratio, insulation thickness and TSV spacing, on thermal-mechanical reliability were analyzed for single TSV, paired TSV and 3*3 TSV array structures. Secondly, a configuration of TSV regular hexagonal array in silicon interposer is proposed to improve its heat dissipation performance.Our simulation results disclose that the stress is mainly concentrated at the junction where SiO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> layer deviates to copper and silicon substrate deviates to SiO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> , which indicates the SiO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> layer is most prone to fracture. The through hole radius should be designed as small as possible to reduce the thermal stress, and a thicker SiO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> insulation layer thickness will induce the better thermal-mechanical stability of TSV. The optimized TSV's depth to width ratio should be set above 5 with the simultaneous consideration of the stress for silicon substrate, insulating layer, filled copper. For multiple TSVs, the spacing should be greater than twice the diameter to eliminate the influence of thermal stress between TSVs. In addition, in the case of the same spacing, the equivalent unit temperature of TSV regular hexagonal array distribution is 2.9°C lower than that of conventional matrix array distribution. The analysis and design of TSV array in 2.5D silicon interposer is promising to offer guideline to the future advanced package development.