Thermal Stresses Analysis of 3-D Interconnect

Abstract

In 3‐D interconnect structures, process‐induced thermal stresses around through silicon vias (TSVs) raise serious reliability issues such as silicon cracking and performance degradation of devices. In this study, the thermo‐mechanical reliability of 3‐D interconnect was investigated using finite element analysis (FEA) combined with analytical methods. The thermal stress in silicon was found to decrease as a function of distance from an isolated TSV but increase with the TSV diameter. Additional simulation results demonstrated that hybrid TSV structures can significantly reduce thermal stresses. An analytical solution was introduced to deduce the stress distribution around an isolated TSV, which was applied to deduce the stress interaction in TSV arrays based on linear superposition of the analytical solution. The stress interaction is directional dependent, thus the TSV array configuration can be optimized to improve the keep‐away‐zone design for stress‐sensitive devices.