Thermal stress reduction of GaAs epitaxial growth on V-groove patterned Si substrates* *Project supported by the National Natural Science Foundation of China (Grant Nos. 61874148, 61974141, and 61674020), the Beijing Natural Science Foundation, China (Grant No. 4192043), the State Key Laboratory of Information Photonics and Optical Communications (Beijing University of Posts and Telecommunications), China (Grant No. IPOC2018ZT01), and the 111

Abstract

We investigate the thermal stresses for GaAs layers grown on V-groove patterned Si substrates by the finite-element method. The results show that the thermal stress distribution near the interface in a patterned substrate is nonuniform, which is far different from that in a planar substrate. Comparing with the planar substrate, the thermal stress is significantly reduced for the GaAs layer on the patterned substrate. The effects of the width of the V-groove, the thickness, and the width of the SiO2 mask on the thermal stress are studied. It is found that the SiO2 mask and V-groove play a crucial role in the stress of the GaAs layer on Si substrate. The results indicate that when the width of V-groove is 50 nm, the width and the thickness of the SiO2 mask are both 100 nm, the GaAs layer is subjected to the minimum stress. Furthermore, Comparing with the planar substrate, the average stress of the GaAs epitaxial layer in the growth window region of the patterned substrate is reduced by 90%. These findings are useful in the optimal designing of growing high-quality GaAs films on patterned Si substrates.