Abstract
The thermal stress due to the thermal expansion mismatch could induce crystallographic defects such as buckling and cracking and degrade device performance. In this paper, the thermal stress distribution in a laser array structure selectively grown on V-groove-patterned Si substrates was investigated by two-dimension finite-element method. Surprisingly, unexpected results are observed that the top of the InGaAs active layer and the most region of the InP cap layer are in compression, which is far different from the thermal stress distribution in planar structures. Two mechanisms have been proposed and modeled to explain the difference—(i) the width of uncoalesced layers is smaller than that of the Si substrate, which causes thermal stress to change in epitaxial layers, and (ii) thermal stress in the InGaAs and InP layers is affected by the V-groove structure. The results show that whether or not the epitaxial layers are coalesced has significant effect on the thermal stress distribution. The effect of the height of the V-groove, the height and the width of the SiO2 mask on the thermal stress distribution was also studied. It is found that the height of V-groove and the height of SiO2 mask play a critical role in the stress distribution. These findings are useful for the optimal designs for the laser array and provide an important step towards the realization of photonic integration circuits on silicon.
Highlights
Integrating III–V compound semiconductors on silicon-based platform to achieve high performance and energy-efficient optoelectronic device such as solar cells,[1,2] photodetectors[3,4] and lasers[5,6] has attracted great interest in the past several years
Unexpected results are observed that the top of the InGaAs active layer and the most region of the InP cap layer are in compression which is far different from the thermal stress distribution in planar structures
Unexpected results are observed that the top of the InGaAs active layer and the most region of the InP cap layer are in compression, which is different from the thermal stress distribution in planar structures
Summary
Integrating III–V compound semiconductors on silicon-based platform to achieve high performance and energy-efficient optoelectronic device such as solar cells,[1,2] photodetectors[3,4] and lasers[5,6] has attracted great interest in the past several years. Considerable difficulties which inhibit the development of the integration of III–V compound semiconductors and silicon need to be overcome. When directly growing III–V semiconductors on silicon, the mismatch of lattice constant, the difference of thermal expansion coefficients and the different polarity between III–V materials and silicon lead to a high density of crystalline defects, such as misfit and threading dislocations, stacking faults, twins, and anti-phase boundaries (APBs), which can greatly degrade the performance and reduce the lifetime of fabricated devices.[7] So far, many planar growth methods have been proposed and taken to overcome these issues, such as the two-step or three-step growth method,[8,9] thermal cycle annealing,[10] buffer layer method,[11] strainedlayer superlattices (SLSs)[12] and dislocation filter with quantum dots.[13] these methods could
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