Thermal stress probing the channel-length modulation effect of nano n-type FinFETs

Abstract

The 3D FinFETs deed provide the impressive gate controllability, especially in drive speed of transistors. However, this advantage relatively brings some drawbacks in channel length modulation (CLM) causing the difficulty in device model establishment. In this work, besides the study of n-type FinFETs in CLM effect, the previous study in 2D HK/MG nMOSFETs at room temperature is also referred and discussed with 3D FinFETs. The influence to the CLM effect at low gate bias is more apparent, speculating the quality of surface channel contributing the depletion width near drain site. The depletion width is usually influenced by raised temperature. And the CLM effect is gradually moved from the low-field dominated to the mid-field as the temperature increased at short-channel device no matter what the VT implant energy is, but not suitable to the others.