Thermal stress induced by the adhesion topology of a semiconductor integrated circuit package

Abstract

In the semiconductor integrated circuit (IC) package, the top surface of the silicon chip is directly attached to the lead frame by a double-sided adhesive layer. Under the functional operation, the IC package has been known to encounter such thermomechanical failure as delamination. This failure is due to the thermal residual strain and stress of the adhesive surface on the silicon chip in the curing-cooling process. The induced thermal effects in the curing process affect the fatigue life of the IC package. Thus, it is necessary to reduce the thermal stress induced on the silicon chip. In this paper, to reduce the surface failure and improve the durability of the silicon chip, the adhesive topologies and thermal stresses on the silicon chip at curing temperature are studied by finite element analysis (FEA).