Thermal Stress and Failure Location Analysis for Through Silicon via in 3D Integration

Abstract

AbstractThrough silicon via (TSV) is the critical structure for three dimensional (3D) integration, which provides vertical interconnection between stacking dies. In TSV structure, large coefficient differences of thermal expansion exist between silicon substrate, dielectric material, and filled metal. Due to the large thermal mismatch, the high thermal stress occurring at the interface of different materials would result in delamination. Therefore, thermal-mechanical reliability is a key issue for 3D integration. In this study, we investigated the thermal-mechanical stress distribution of TSV under the condition of the accelerated thermal cycling loading by finite element analysis based on a 3D model of TSV structure. Due to the thermal expansion, that the TSV structure squeezed the surface area between TSVs at a high temperature resulted in compressive stresses at the surface area between TSVs. Therefore, a proper distance between the stress-sensitive device and the TSV should be kept. The stress analysis shows that the maximum thermal stress occurs in the outside region of TSV interface and in the annular region of TSV at a high temperature and at a low temperature, respectively. This study helps to obtain a clear thermal stress distribution of TSV and possible failure regions can be determined.