Thermal stress and drop stress analysis based on 3D package reliability study

Abstract

As the semiconductor industry enters the post-Moore era, chip packaging is gradually developing in the direction of miniaturization, multi-function and low power consumption, which has prompted the creation of three-dimensional packaging. The thermomechanical stress and drop stress of 3D package are relatively large, which is very different from the common packaging method. In this paper, an equivalent layer is introduced, a quarter model is constructed and a series of changes in the chip during use due to the influence of the external environment are simulated using ANSYS focusing on the warming process and dropping from different heights. The total deformation, maximum principal stresses and equivalent forces are simulated during the temperature increase of the packaged chip from 22 °C to 280 °C and after falling from the heights of 1 m, 2 m and 3 m. Results show that the parts of the overall model that are more prone to failure in the case of heating or dropping are the four corners of the bottom chip, the copper pillar at the center of each copper pillar array, the upper surface of the bottom equivalent layer and the four corners. To improve the reliability of the packaged chip, the above mentioned areas of the packaged chip must be strengthened first.