Abstract

With the increasing of packaging integration the power and the quantity of heat of integrate circuit will increase, it will bring more and more temperature distributions and problems about thermal stresses in package. In this paper a finite element thermal stress model of substrate-adhesive-chip is established, thermal stress distribution of substrate-chip interfaces and the affects of geometrical structure on thermal stresses are analyzed by finite element method, especially discuss interfacial thermal stresses distributions on chip-adhesive interface and adhesinve-substrate interface.

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