Abstract
AbstractWe consider a thermal model for an integrated circuit including its chip environment. As the simplest choice, the active device layer (integrated circuit) consists of an array of replicas of the same quantum device with the same time depended average temperature. Modeling the chip environment we assume this active layer is sandwiched between two coplanar heat reservoirs. The top heat reservoir represents the wiring layer of the chip (‘back‐end of line’). Its temperature is predominantly determined by the dissipated Joule heat in the wiring, typically in the order of one hundred degrees of Celsius.The bottom reservoir represents the cooling unit at about room‐temperature. We solve the coupled equations describing thermal transport between the active layer and surrounding heat reservoirs and electrical transport in the quantum devices. The stationary working temperatures of the considered quantum devices can be found from a fix‐point problem. A proper linearization of the complete time‐depended problem yields the stability of these fixpoints. Numerical solutions for a device layer consisting of identical nano‐transistors are given for selected parameters.(© 2014 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)
Published Version
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