Thermal preprocessing to shorten flows, simplify lithography, and radically reduce processing cycle time

Abstract

In integrated circuit (IC) manufacturing, mismatch in processing times (about one minute per wafer for some steps to over ten hours per wafer for others) forces grouping of wafers into lots and batches for economic processing. If separation through implanted oxygen (SIMOX) silicon-on-insulator (SOI) wafer production was followed by blanket gate oxide growth and poly silicon deposition before the wafers entered the semiconductor fabrication process, processing could start with the critical lithographic step, poly-silicon patterning, thereby avoiding overlay issues. This step could be followed by source/drain formation, and rapid-thermal-annealing (RTA) to activate the implants and a shallow trench to the buried oxide for isolation. This would complete the front-end processing with no need for long thermal steps. The result would be simplified lithography, reduced process flow length, and better matched processing times facilitating more complete clusterization of the factory and, thereby, a radically reduced cycle time. The cycle time using this approach is expected to be on the order of one day, accelerating yield learning, reducing inventory risks, and reducing processing overhead in cleans and inspections.