Thermal perspective design Analysis of 3D stacked chip integrated by TSV, Micro-bump and TMV with SOC

Abstract

In this paper, a design analysis considering the thermal characteristics of SOC (system on chip) 3DIC (three dimensional integrated circuit) structure is presented. More complex, multiple and complicated functions are being required to be integrated in one package for small form-factor and low power. Since the heterogeneous integration by using multiple semiconductor fabrication processes can give several benefits including power reduction, yield and cost, three-dimensional (3D) integration with multiple stacking chips is promising solution. In the case of 3DIC, there are some structural differences from the existing mono chip in SOC package. There are micro bumps for electrically connecting the top and bottom chips, a through silicon via (TSV) inside the bottom chip to connect the top chip signal to the package substrate, and a through mold via (TMV) that connects through the outside of bottom chip. If the thickness of the silicon chip becomes thinner by stacking, the power density increase. As a result, the heat diffusion performance through silicon is lowered compared to mono chip, which causes the temperature to increase. Therefore, in order to improve the thermal properties of stacked chip, we analyze the micro-bump, TSV and TMV design which are the main factors affecting the thermal characteristics of 3DIC structures, and propose an optimal 3DIC design that can minimize temperature by thermal analysis through simulation.