Thermal modeling and characterization of Package with Through-Silicon-Vias (TSV) Interposer

Abstract

Numerical simulation of micro-bumped flip chips mounted on a TSV interposer is conducted to study the thermal performance of the package. The 3D package, which consists of two chips, each dissipating 4W, is evaluated under various conditions with its thermal resistances θ ja θ jb , θ jc and θ jma determined according to JEDEC or MIL-STD standard. Instead of building the detailed model, equivalent thermal conductivity model is adopted for anisotropic bump-underfill layers, silicon interposer and the substrates. Effects of design parameters to the waste heat dissipation, such as the density of TSV in the interposer and the presence of mold encapsulation are investigated. In addition, maximum power dissipation of the package is explored. These modeling results are useful for design optimisation, and also to provide thermal design guideline for a reliable, high performance, and cost-effective 3D package.