Abstract
As market for High-Performance Computing (HPC) grows and demands for high performance memory device increases, it is becoming more important to predict the thermal characteristics of High Bandwidth Memory (HBM) at the design stage. However, accurate prediction of HBM temperature has been limited due to the complexity of the 3D stacked structure of HBM and diverse external thermal conditions at system level. Furthermore, the HBM stack thermal resistance becomes more crucial as the power of HBM increases, which highlights the importance of accurate prediction of the stack thermal resistance. In this research, we develop HBM thermal model in SiP system based on the measurement results. In order to investigate thermal characteristics, we experimentally demonstrate the thermal behavior of the HBM in SiP system that consist of two ASIC with eight HBMs. Furthermore, a standard methodology is proposed to evaluate stack thermal resistance which is one of main parameters to build the thermal model of multi-chip 3D stacked package. The thermal model shows 97% accuracy temperature prediction in the SiP level simulation.
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