Thermal impact of 3D stacking and die thickness: Analysis and characterization of a memory-on-logic 3D circuit

Abstract

Heat dissipation is assumed to be one of the major challenges in the promising 3D integration technology due to its higher power density and reduced heat dissipation properties when compared to a traditional single-die fabrication process. This work brings a discussion of the main aspects differentiating heat dissipation in 3D ICs. A complete system including packaged IC, socket and board is used to evaluate the thermal impact of a stacked memory die. Simulation and experimental temperature data from two versions of a thermal test circuit are compared to reveal the thermal profile changes resulting from the 3D integration. The first circuit version is a 65nm SoC instrumented with heaters and thermal sensors. The second version has a WideIO compatible memory stacked on top of the same SoC, resulting in a memory-on-logic 3D circuit. This work also investigates the thermal impact of chip footprint, die thickness and die-to-die interface parameters using explorative thermal simulations. Results show that while thinned silicon dies required for TSV integration may result in exacerbated hotspots due to reduced lateral heat spreading capacity, non-thinned stacked dies may act as heat spreaders and help to mitigate thermal issues in 3D ICs. The discussion presented in this work aims to understand the thermal impact of technology parameters inherent in 3D integration and support system architects and designers to take early design decisions and prevent thermal issues.