Thermal annealing effects on the electrical characteristics of the back interface in nano-silicon-on-insulator channel

Abstract

The electrical properties of the back interface between the thin silicon and buried-oxide layers of nano-silicon-on-insulator substrate were evaluated. The effects of rapid thermal annealing (RTA) process were investigated, and the distributions of interface states at the thin silicon/buried-oxide interface were estimated by using metal-point-contact field-effect-transistor method. The interface-states at the back interface were considerably increased by RTA process. The RTA higher than 800°C contributes to the increase of acceptor-type interface states. The increased interface states were effectively reduced by conventional furnace annealing at 500°C in nitrogen ambient.