Abstract
Temperature distributions in SOI transistor devices with trench isolations in LSI chips were calculated using three-dimensional computer simulations. The relations between the maximum temperature increase in transistor devices and the geometric parameters (width and length of aluminum lines on the transistor devices, size of SOI regions, and spacing of two SOI devices) were calculated. We also calculated the effect of placing a heat dissipation layer on the SOI devices. Temperature increases in SOI devices were measured by placing a thermal sensor diode in the SOI region. The calculation results and experimental results agreed well. The calculation results can be used for optimal thermal design of SOI devices in LSI chips.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
More From: TRANSACTIONS OF THE JAPAN SOCIETY OF MECHANICAL ENGINEERS Series B
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.