Abstract
A new theory of single event latchup in complementary metal-oxide semiconductor (CMOS) integrated circuits is described. The temperature effect on both cross section and critical linear energy transfer (LET) is explained. The latchup cross section is related to a characteristic length, which is based on the lateral transistor parameters. In this way, the large increase in cross section with temperature is explained. The LET threshold is dependent on the depletion width of the n-substrate p-well junction, which is relatively independent of temperature.
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