Theoretical Study of the Gate Leakage Current in Sub-10-nm Field-Effect Transistors

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Scaling field-effect transistors (FETs) with conventional semiconductor channels requires a reduction of the body or fin thickness or of the diameter of the nanowire (NW) channel. We present a theoretical study showing that the increase of the ground-state sub-band energy induced by the quantum confinement associated with this scaling results in a dramatic reduction of the barrier at the channel/gate-insulator interface, which causes an increase of the leakage current across the gate insulator. We have studied the problem using scaling rules extracted from the 2011 International Technology Roadmap for Semiconductors (ITRS)-Roadmap (finding them excessively relaxed) and using more strict scaling rules from the literature confirmed by simulations of 5-nm gate-length III-V FETs. Employing local empirical pseudopotentials to calculate the electronic structure of Si and InAs thin bodies, the leakage gate current in the ON-state is shown to reach worrisome values at gate lengths of about 5 nm. This suggests that 1-D channels (i.e., NWs), but especially channels based on intrinsically 2-D (e.g., graphene/graphane or transition-metals dichalcogenides) or 1-D (e.g., carbon nanotubes) structures, are required to push scaling toward the 5-nm node.