Theoretical predictions of EM-induced degradation in test-structures and on-chip power grids with analytical and numerical analysis

Abstract

Paper discusses the state of the art physics-based analytical modeling and numerical analysis techniques developed for the prediction and description of electromigration (EM) induced conductance degradation of individual interconnect metal lines and on-chip power grids. Mechanical stress evolution caused by an electric current driven redistribution of vacancies and plating atoms, which populate the metal grain boundaries (GB) and interfaces, initiates the growth of preexisted crystal imperfections such as micro cavities and interfacial/inter-granular delaminating. It is described as a major cause of the failure. A role in the failure development played by the interfacial and GB atomic diffusions and their variation is covered. A close relation between the interfacial-adhesion energy and so-called “critical stress” is clarified. A physics-based statistical formulation of EM phenomenon is discussed. Different kind of analytical/numerical techniques employed for analysis of EM degradation in different cases characterized by the scales varying from the size of an individual line to the multibillion segment power grids are discussed. Conditions for employment of 1D EM approximation (Korhonen's equation) are validated by direct comparison with results of 3D FEA simulations. Implementation of the novel compact model- and FDA-based approaches for analyzing EM-induced IR-drop degradation in power nets is demonstrated.