Novel methodology for temperature-aware electromigration assessment in on-chip power grid: simulations and experimental validation (Invited)

Abstract

A novel methodology for electromigration (EM) failure assessment in power/ground nets of integrated circuits, which is based on analysis of IR drop degradation, has been enhanced by considering non-uniform temperature distribution in interconnects. Temperature gradient along an interconnect tree can affect void nucleation due to the divergency of atomic flux, as well as due to development of thermal stress. Compact models for resistance increase of voided metal have been developed, using results of FEM simulations of voiding kinetics in via-metal structures. The simulation approach has been validated using measurements of node voltages in a specially designed test power grid. Increase of anode-cathode voltage drop above a threshold value was adopted as a failure criterion determining time-to-failure (TTF) of the grid and mean-time-to-failure (MTTF) was obtained, assuming random distributions of the critical stress and atomic diffusivity. In the studied cases of temperature distributions, a good agreement of simulated and measured TTF distributions has been obtained.