Abstract
A new inverter topology is presented in the paper, which produces a reduced low-order harmonic voltage waveform because of a natural harmonic cancellation process. Two switches of each limb operate at low switching frequency, whereas the other two switches of the same limb operate at higher switching frequency in conjunction with two additional capacitors. The four switches in each limb are controlled in such a way that the sequence of switching along with the voltage of two additional capacitors cancels out the low-frequency harmonics, thereby creating a pulse-width modulation (PWM) voltage with reduced low-order harmonics at the output with respect to the dc midpoint. By selection of the PWM pattern, the magnitude of fundamental voltage produced at the output can be higher than what would be achieved using sinusoidal PWM from the same dc bus voltage, without bothering about its inherent lower-order harmonics as they would be anyway cancelled. It is thus possible to achieve maximum possible dc bus utilisation theoretically.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
