Analysis of Symmetric and Asymmetric Multilevel Inverter Topologies Using Reduced Number of Switching Devices Circuit Structure

Abstract

This paper presents symmetric and asymmetric multilevel inverter principles using reduced number of switching devices circuit structure. Principally, asymmetric multilevel inverter topology able to produce higher output voltage level without modification of the structure in order to reduce total harmonic distortion at the output voltage. In contrast, the number of switching devices need to be increased with symmetric principle when higher output voltage level is considered. In this study, 5-level reduced number of switching devices circuit structure is selected as a circuit configuration for symmetric (5-level structure) and asymmetric (7-level and 9-level structures) multilevel inverters. For switching strategy, modified pulse width modulation and sinusoidal pulse width modulation are selected to produce output voltage levels of the inverter. Modified pulse width modulation used low switching frequency in producing signal and needs higher output voltage levels to achieve low total harmonic distortion. In contrast, sinusoidal pulse width modulation used high switching frequency in order to minimize total harmonic distortion. Theoretically, total harmonic distortion is reduced when number of output voltage level is increased for both cases. The findings show that, the 9-level asymmetric topology has lower total harmonic distortion compared to the 5-level symmetric topology and 7-level asymmetric topology, whereby these inverters using the same circuit configuration. The results show that, the total harmonic distortions of 9-level asymmetric topology, 7-level asymmetric topology and 5-level symmetric topology are 14.54%, 18.08% and 26.92%, respectively with sinusoidal pulse width modulation switching strategy. Meanwhile, with modified pulse width modulation switching strategy, the total harmonic distortions of 9-level asymmetric topology, 7-level asymmetric topology and 5-level symmetric topology are 18.7%, 21.68% and 28.99%, respectively. Therefore, 9-level asymmetric with sinusoidal pulse width modulation switching strategy show the lowest total harmonic distortion with optimum number of switching devices.