The Thermal Integrity of Integrated GaN Power Modules

Abstract

In this paper the authors describe GaN (gallium nitride) power switching transistors that use copper post and substrate via interconnect techniques. These transistors can be matrixed to allow a parallel array of the devices to provide very low on-resistance and high operating voltages. At 150 °C the basic building block which is a 2 × 2 mm die, provides 1200 V / 14 A. A 2×2 matrix array of these transistors provides for example, 1200 V / 56 A operation. The overall GaN device size is 4 × 4 mm. This high current density is achieved by using a unique castellated island topology. This provides short fingers that are not required to carry high current. No high current tracks are provided on-chip because on-chip metal is typically less than 3 microns thick. The die has 12 copper posts on the source islands that carry the current to the CMOS driver device. The CMOS driver is used in a cascode configuration which allows the normally-on GaN transistor to be operated with convenient normally-off functionality. The two devices are combined in a modular assembly. The paper provides a thermal analysis of the assembly. The objective of the design is to keep the ‘junction’ temperature of the GaN transistor below 150 °C.