Abstract
It is a common belief that a noise-free frequency divider by D scales down the input phase by a factor of 1/D, thus the phase-noise power spectral density (PSD) by 1/D <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . We prove that the behavior described does not apply to digital dividers. Instead, the digital divider scales the white phase-noise PSD down by 1/D. Phase downsampling and aliasing, inherent in digital frequency division, is the reason. However the 1/D <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> law holds asymptotically for flicker, where the aliases can be neglected. We propose a new de-aliased divider, which scales the input phase-noise PSD by approximately 1/D <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The scheme is surprisingly simple and suitable to CPLD and FPGA implementation.
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