Power supply noise conversion to phase noise in CMOS frequency digital divider

Abstract

A digital frequency divider is a state machine that synthesizes a frequency sub multiple of a reference signal. While the digital frequency divider is a digital circuit handling square waves, its input and output signals are usually sine waves; a sine wave to square wave front-end circuit is required to generate an appropriate clock signal for the flip flops in the divider. In the first approximation the gate threshold voltage changes with power supply voltage and this voltage noise yields symmetrical duty cycle modulation of the gate output square-wave signal; that is, if it makes rising edges anticipate then the failing edges are delayed. Although zero crossing jitter is present, the sine wave signal obtained by filtering out the harmonics of the square wave fundamental component is amplitude modulated only and no phase modulation occurs. The picture changes when the square wave signal goes to a selective front edge digital processor as a digital frequency divider, where rising or failing edges are used only. The divider output signal loses the duty cycle symmetry and the entire waveform is jittered because of the power supply voltage changes. This results in phase modulation and therefore a power supply to phase sensitivity.