The role of velocity saturation in the switching delay of an R-C loaded inverter

Abstract

Exact analytical expressions for the switching delay of an inverter driving an RC load, taking into account the velocity saturation, are obtained. Modified expressions to include the effect of source resistance are then presented. Owing to the limitation on switching current imposed by the velocity saturation mechanism, the switching delay is substantially increased for identical width-to-length ratios of the MOSFET in a complementary MOS logic circuit. Obviously, it is important to increase the saturation velocity by miniband engineering or otherwise to improve the performance. However, it is found that the improvements in the time delay are marginal after a saturation velocity of 2.4*107 cm s-1 is reached. The effect of technologies aimed at circumventing the hot-electron and other deleterious effects is a longer delay time of the circuit due to increased series resistance. However, the effect of increased series resistance is substantially damped due to velocity saturation. These results are particularly important in designing CMOS circuits with submicrometre MOSFET dimensions.