The role of process and geometrical parameters of gate stack Inverted-T shape junction less FET at 20 nm technology node

Abstract

In the present era, FET devices are seamlessly integrated with complex circuits that can be used to realize chips capable of operating at a significantly higher speed. These designed devices can meet the requisite of circuits used in designing mobile phones, tablets and laptops, thereby enhancing the overall performance. The present work focuses on designing of gate stack inverted-T junctionless FET at 20 nm technology node. Both static and low frequency characteristics of device such as threshold voltage (VTh), transconductance (gm), on (ION) & off (IOFF) state currents, as well as its high-frequency characteristics like total gate capacitance (Cgg), cut-off frequency (fT), maximum oscillation frequency (fmax) and gain bandwidth product (GBW) are methodically demonstrated with alterations in the device process and geometrical variations. The parameters such as height of fin, width of fin and work function are varied to study their impact. The SS, DIBL, ION/IOFF (current switching ratio) and VTh, for 20 nm gate length are observed as 67.94 mV/dec, 34.32 mV/V, 108, 0.32 V, respectively. The fmax is determined to be in the THz range and has early voltage of approximately 6.12V. Additionally, the effect of temperature is also studied by varying it in the range of 250 K–450 K. Analysis and virtual modelling of device is carried out using Visual TCAD. In addition, p-channel transistor is designed along with the n-channel configuration to investigate the device performance for CMOS based circuits. The noise margin and average delay of the inverter circuit are observed to be 0.37 V and 36.7 ps respectively.