Abstract
In DRAM products, the copper interconnections with larger grain size are preferred for lower electrical resistance and better circuit performance. We studied the copper properties which are the evolution of the grain size, distribution of the grain, and the metal line texture formation during self-annealing. And we were able to evaluate the thermal budget in the DRAM process by performing thermal excursion stress test. We found out that the condition with self-annealing time affects copper grain size and stress migration. It has been measured by the EBSD analysis system and TOF-TEM. Compared with the conventional copper anneal process which has no time delay, the self-annealing process with time delay showed the more bamboo microstructure at dram damascene process. In addition, we observed that the self-annealing process helped enhanced thermal stress stability, which is caused by lower hillock deformation to copper top surface after a batch furnace at 400°C, N2 ambient for three times.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.