Assessing merged DRAM/Logic technology

Abstract

This paper describes the impact of DRAM process on the logic circuit performance of Memory/Logic Merged Integrated Circuit and the alternative circuit design technology to offset the performance penalty. Extensive circuit and routing simulations have been performed to study the logic circuit performance degradation when the merged chip is implemented on DRAM process. Three logic processes ( 0.5, 0.6 and 0.8 μm) and two corresponding contemporary DRAM (64 and 256 Mb) processes have been selected for the study knowing that the performance difference between the logic and DRAM processes can be extrapolated for the advanced processes. The simulation results show that the logic circuit performance is degraded by about 22% on DRAM process including the increased interconnect delay due to less interconnect layers available in the DRAM process. The silicon area is increased up to 80% depending on the number of net and components when implementing a logic circuit in a DRAM process. Simulation results show that the performance penalty can be well offset if the same circuit used in the simulation is implemented using dynamic circuit techniques.