The Resistance of Grain Boundaries in BaTiO<inf>3</inf>-Based Ceramic

Abstract

Evidence for grain boundary (GB) resistance in BaTiO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</inf> based capacitor ceramic exists in superohmic current voltage characteristics, in voltage-dependent activation energies, in high-voltage ohmic behavior, and in a conductivity peak at the Curie temperature. These phenomena are reviewed. Impedance-frequency measurements are reported for GB-controlled varistors and for BaTiO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</inf> -based capacitor ceramic under increasing voltage bias. The impedance plots are discussed in terms of grain and GB contributions. No contribution from contacts is evident. The resistance attributed to GB decreases faster with voltage bias than that due to grains. Schö11's model for dependence of GB barrier height on grain curvature for polycrystalline silicon is adapted to high-K ceramic. It is seen that grain curvature, along with carrier depletion in the grains, can result in significant reductions in GB barrier height and hence resistance. Variation in grain size in a given ceramic can result in GB resistance variations throughout the material.