The Reliability of Solder Joints in Fine Pitch 3-D Stack Package by Taguchi Method

Abstract

To achieve high density and high performance, through-Silicon Vias (TSVs) have recently aroused much interest because it is a key enabling technology for three-dimensional (3-D) integrated circuit stacking and silicon interposer technology. In this study, a 3-D 1/8th symmetrical nonlinear finite element model of a stack die TSV package was developed using ANSYS finite element simulation. The model was used to optimize the package for robust design and to determine design rules to enhance 3-D stack package in view of bump reliability. An L8(2×7) Taguchi matrix was developed to investigate the effects of interposer thickness, TSV diameter, insulation (SiO2) thickness, chip thickness, substrate thickness, bump height, and bump diameter on bumps reliability. A temperature cycling test in the range of 0 °C to 100 °C was conducted by three cycles. The mechanical property of SAC leadless solder included time independent plastic and time dependent creep behaviors. The parameter of inelastic strain range of the third cycle was used to evaluate the bump life prediction. Two levels were chosen for each parameter to cover the ranges of interest. The results show that the smaller insulation (SiO2) and substrate thickness and the larger dimension for the other factors provide the best combination. These could be used as guides for further similar 3-D stack packages design.