Parameter study to the interposer stress analysis of fine pitch 3-D stack package

Abstract

Through-Silicon Vias (TSVs) have recently aroused much interest because it is a key enabling technology for three-dimensional (3-D) integrated circuit stacking and silicon interposer technology. In this study, a 3-D 1/8th symmetrical nonlinear finite element model of a stack die TSV package was developed using ANSYS finite element simulation code. The model was used to optimize the package for robust design and to determine design rules to enhance TSV reliability in view of TSV stress. An L 9 Taguchi matrix was developed to investigate the effects of dielectric thickness, TSV diameter, and interposer thickness on TSV stresses that could possibly occur during a temperature cycling test in the range of 0 °C to 100 °C. The TSV stress index was based on the end of high-dwell temperature in the third cycle due to a 75 °C temperature difference compared with room temperature of 25 °C. Three levels were chosen for each parameter to cover the ranges of interest. The results show that the best combination is 1 μm of insulation thickness, 50 μm of TSV diameter, and 400 μm of interposer thickness. The sensitivity degree order of system noise is interposer thickness, TSV diameter, and dielectric thickness. These could be used as guides for further similar 3-D stack packages design.