The Reliability of LTPS-TFTs Alternately Stressed in OFF Region

Abstract

The reliability of n-channel low temperature poly-Si thin film transistors (LTPS TFTs), which are dynamically stressed in OFF region with drain zero biased and source grounded, is investigated. Rectangular pulses with different parameters such as rising time, falling time or frequency are imposed to the gate electrode to examine the degradation. It is observed that the degradation depends strongly on the rising time and frequency of ac signal. As the gate voltage switches in the rising period, the accumulated holes should be swept out and flow into source or drain terminals, owing to the floating body structure of TFTs. Therefore, there is high electric field at the rising period of transient stress, which enhances the degradation. A degradation model is proposed to explain the degradation mechanism of LTPS TFTs on the basis of the flowing direction of the sampling current Id, and demonstrated by two electrical measuring items, saturation forward & reverse Id-Vg transfer curves and C-V curves.