Abstract
The holding point for CMOS latchup has been studied empirically and analytically using a semiconductor device physics code. A relationship between holding current and voltage has been identified that shows variations in doping, layout, epitaxy, and temperature produce different holding points that all fall on the same I-V curve. Analysis of the fields and carrier densities within negative resistance has provided new insight into the latchup response. A general solution for voltage as a function of current, valid at all points above switching, has been derived based on fields and carriers. The solution explains the relationship of holding points observed in empirical data. >
Published Version
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