Abstract
The design complexity of systems on a chip drives the need to reuse legacy or intellectual property cores, whose gate-level implementation details are unavailable. In this paper we consider the realization-independent testing and the impact of circuit realization on the fault coverage. We investigated two fault models (input-output pin pair fault and input-input-output pin triplet fault) that are used by test generation for circuits described at system description level. The test generation on the system-level model is preferable if the efforts and the duration of the test supplement activities are less than the efforts and the duration of the test generation on gate-level model. The test set for the black-box model is larger as compared to the test set for the particular realization of the circuit. However, large test sets for the black-box model can be compacted by analysis not only according to the stuck-at faults, but also according to various defects for the particular realization.
Highlights
As a result of modern technologies both the digital device density and the device complexity have steadily increased
We see that the test sets for the pin pair faults (PP) faults and for the supplemented test sets detect less stuck-at faults for the original realization R1. It may be explained in such a way: the original circuits were synthesized early and re-synthesized by Synopsys the benchmark circuits are more optimized and have less stuck-at faults. It means that the fault coverage of the test sets generated for the black box model depends on the optimization level during the synthesis of the circuits
The test generation on the system-level model is preferable if the efforts and the duration of the test supplement activities are less than the efforts and the duration of the test generation on gate-level model
Summary
As a result of modern technologies both the digital device density and the device complexity have steadily increased. What is needed is a design, a test methodology and fault models that may enable a high-level design validation, the testability enhancement and the test generation in such a way that a high Defects Coverage (DC) is achieved Reaching this goal independently from the structural synthesis and from the manufacturing technology is impossible, as the test quality will always depend on the final physical realization. Tests for stuck-at faults cover real defects of the layout only for primitive (not complex) gates In this case we are speaking about the layout-independent test generation. The test generation task is much more complicated, but it can be done in parallel with the design of the synthesizable description and with the synthesis of the circuit on the gate level (Fig. 1). In this paper we consider the realization-independent testing, investigate the impact of the circuit realization on the fault coverage of the test set, the suitability of black-box fault model for the testing of different realizations and the capabilities of the test generation for the black-box model
Sign-in/Register to view highlights & summary Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
