The prototype of the 4<sup>th</sup> generation single FPGA Front-End Boards with 100 MHz sampling and DCT spectral trigger for Auger surface detectors

Abstract

The surface detector array of the Pierre Auger Observatory contain 1600 water Cherenkov detectors spread over an area of 3000 km <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The Cherenkov light is detected by three 9-inch photomultiplier tubes from which the signals of the anode and last dynode are digitized by 10 bit ADCs. The currently used generations of the Front-End Boards equipped with the ACEX <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">®</sup> and Cyclone™ chips were sampled with 40 MHz clock. New requirements from the Auger North (100 MHz) and AMIGA (80 MHz) specification as well as proposal of new spectral triggers based on the 16-point Discrete Cosine Transform (DCT) requires a new Front End Boards with more powerful FPGA chip. The DCT trigger can be only implemented in a newer FPGA chips supported by sufficient amount of DSP blocks. The DCT trigger allows recognition of ADC traces with a very short rise time and fast exponential attenuation related to a narrow, flat muon component of very inclined extensive air showers generated by hadrons and starting their development early in the atmosphere. The DCT based on only real coefficients in the frequency domain, provides much more sensitive trigger conditions and a simpler interpretation in comparison to a discrete Fourier transform (DFT) that is based on complex coefficients. It also offers a scaling feature. The ratio of the DCT coefficients to the 1 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">st</sup> harmonics depends only on the shape of signals, not on their amplitudes. 10 prototype boards equipped with Altera <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">®</sup> CycloneIII™ FPGA have been fabricated and successively tested in the lab and in real pampas conditions in six test surface detectors within April 19 - July 26, 2009. Boards contain only a single FPGA chip, which implements also the slow channel, in previous three generations supported by the external Dual-Port RAM. Tests confirmed full stability and high reliability of the digital part. Both lab and field tests confirm a high efficiency of the recognition of expected patterns of ADC traces.