Abstract

In this paper, we have described the complementary metal–oxide–semiconductor (CMOS)/magnetic tunnel junction (MTJ) integrated process technology; MTJs were fabricated on via metal with surface roughness of 0.3 nm with 0.14 µm CMOS process and 60 ×180 nm2 MTJ process. It is shown that by this process technology, the fabricated MTJ on CMOS logic circuit plane achieves a large change in a resistance of 3.63 kΩ (anti-parallel) with the TMR ratio of 138% at room temperature, which is large enough for a sensing scheme of standard CMOS logic. Furthermore, we have successfully demonstrated the DC and AC operation of this MTJ with write transistors. As the results, our MTJ achieves high enough write/read performance with transistors for realizing MTJ-based logic circuits.

Talk to us

Join us for a 30 min session where you can share your feedback and ask us any queries you have

Schedule a call

Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.