The MARS High-Level DSP Synthesis System

Abstract

This paper addresses high-level synthesis methodologies for dedicated digital signal processing (DSP) architectures used in the Minnesota ARchitecture Synthesis (MARS) design system. We present new concurrent scheduling and resource allocation algorithms which exploit inter-iteration and intra-iteration precedence constraints. These novel algorithms implicitly perform algorithmic transformations such as pipelining and retiming, and produce solutions which are as good as or better than those previously published. Previous synthesis systems have focused on DSP algorithms which have single or lumped delays in the recursive loops. In contrast, MARS is capable of generating valid architectures for algorithms which have randomly distributed delays. MARS exploits these delays to produce more efficient architectures and allows our system to be more general. We are able to synthesize architectures which meet the iteration bound of any algorithm by unfolding the original data flow graph.