Abstract
The authors address methodologies for high-level synthesis of dedicated digital signal processing (DSP) architectures using the cluster-oriented and minimum execution time (COMET) design system. The system is tuned to the synthesis of DSP ASICs from behavioral specifications written in VHDL. COMET is capable of generating more efficient architectures using innovative scheduling and resource allocation algorithm which exploit the cluster information and maximize the parallel tasks. With these transformations, major improvements are achieved with fewer registers and interconnections; an industrial quality design is then derived in both FIR and elliptic filter examples. >
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