Abstract
The current LHCb trigger system consists of a hardware level, which reduces the LHC inelastic collision rate of 30 MHz to 1MHz, at which the entire detector is read out. In a second level, implemented in a CPU farm, the event rate is reduced to about 5 kHz. The major bottleneck in LHCb's trigger efficiencies for hadronic heavy flavour decays is the hardware trigger. The LHCb experiment plans a major upgrade of the detector and DAQ system in the LHC shutdown of 2018. In this upgrade, a purely software based trigger system is being developed, which will have to process the full 30 MHz of inelastic collisions delivered by the LHC. Both the current trigger system and its planned upgrade are discussed in these proceedings.
Highlights
The LHCb detector at the LHC is a precision experiment dedicated to beauty and charm physics, covering a rapidity range of 2 < η < 5 [1]
One novel feature of the Run 1 trigger was that of event deferral: 20% of all L0 accepted events were stored on disk to be processed by the High-Level Trigger (HLT) during the LHC inter-fill time, which made an effective 25% of extra CPU available
Changes will be introduced in the architecture: both HLT levels will be split in two separate physical processes, allowing the second stage to run asynchronously
Summary
This content has been downloaded from IOPscience. Please scroll down to see the full text. Ser. 623 012003 (http://iopscience.iop.org/1742-6596/623/1/012003) View the table of contents for this issue, or go to the journal homepage for more. Download details: IP Address: 131.169.4.70 This content was downloaded on 28/06/2015 at 20:29 Please note that terms and conditions apply
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