The large-scale integration of high-performance silicon nanowire field effect transistors

Abstract

In this work we present a CMOS-compatible self-aligning process for thelarge-scale-integration of high-performance nanowire field effect transistors withwell-saturated drain currents, steep subthreshold slopes at low drain voltage and a largeon/off current ratio (>107). The subthresholdswing is as small as 45 mV/dec, which is substantially beyond the thermodynamic limit (60 mV/dec) of conventional planar MOSFETs. These excellent device characteristics are achievedby using a clean integration process and a device structure that allows effectivegate–channel–source coupling to tune the source/drain Schottky barriers at the nanoscale.