Abstract

Phase comparators used in phase-locked loops extracting symbol timing from baseband data waveforms typically only produce a useful error signal when a data transition occurs. This gating of the error signal by data transitions makes the natural model for studying jitter in such phase-locked loops time-varying and difficult to analyze. In this paper we show how, under good approximation, it can be simplified to a time-invariant model that is easily analyzed. Using this model, we study jitter accumulation along chains of digital repeaters with phase-locked-loop timing extractors. A numerical example is given.

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