Single - phase phase locked loop with DC offset and noise rejection capability for photovoltaic inverters in distributed generation

Abstract

Green and sustainable energy could not be realised without stable and reliable grid. When green energy such as photovoltaic (PV), is injected to the grid, it requires accurate synchronization (voltage, frequency and phase angle). This can be done via phase locked loop (PLL). The performance of the conventional PLL is poor due to steady-state error. Moreover, it fails to operate under weak grid condition, i.e., with dc offset and with noise. Although many PLLs have been proposed in the literature to eliminate the steady-state error, the performance of the PLLs under weak grid condition is still poor. In this paper, a new PLL is proposed to eliminate the DC offset and noise. The results show that the proposed PLL is able to completely eliminate the perturbation of 30 % DC bias, 0.095 W of noise, with a settling time of 150 ms. 10% of magnitudes of low order 3rd, 5th and 7th harmonics are also reduced considerably. Furthermore, the under shoot of the estimated frequency waveform is reduced up to 8 Hz. With the proposed PLL, the green energy can be harvested without any grid stability concerns.